The present invention broadly relates to demodulators in general, and to demodulators for high-speed data transmission using clear mode communication methods in particular.
As is well known in communication systems, modulation involves varying a high-frequency carrier wave in a predefined way so that the variations correspond to the information content of an information signal. A new variation to the carrier wave is often introduced to correspond to each new sample of the information signal. In order for a receiver to obtain the information signal, a transmitted carrier wave is demodulated.
While a demodulator may be a discrete circuit, it is typically incorporated in a receiver chip. A clock signal controls the timing of the demodulator. In prior art demodulators, a sample from the received signal can be obtained at a rate up to the maximum clock rate. For example, if the maximum demodulator clock rate is 200 megahertz, the demodulator can demodulate an information signal with a sample rate up to 200 megahertz.
If the information signal sample rate exceeds the maximum clock rate of a prior art demodulator, the demodulator either does not function, or produces a demodulated signal which is not a duplicate of the original information signal, but one that is either interpolated or a low-resolution facsimile. For example, if the information signal is 1.2 gigahertz and the maximum demodulator clock rate is 200 megahertz, a functioning demodulator will produce only 1 for every 6 original samples. While this may be sufficient for some operations, such as when a low-resolution video signal is needed, it is not acceptable for other operations where the demodulated samples need a much higher correlation with the original samples.
The aforementioned problems can be eliminated, of course, by providing a much higher demodulator clock rate. However, the demodulator circuitry would be more expensive. At least with respect to unspread (clear) modes of communication such as Phase Shift Keyed (PSK) or Quadrature Amplitude Modulated (QAM) waveforms, there is a great need to provide a demodulator that can, if needed, demodulate an information signal having a sample rate exceeding the demodulator""s maximum clock rate, while still outputting a demodulated signal with a high degree of fidelity to the original information signal.
In view of the above-identified problems and limitations of the prior art, the present invention provides a method of demodulating data signal waveforms via a demodulator residing in a device. The method at least includes the steps of serially receiving an input waveform with a symbol rate M, converting said input waveform into input vectors, each vector having a predetermined number of samples, and for each device clock period, where the maximum device clock speed is R, processing an input vector by making soft decisions to demodulate said input vectors into output vectors containing data estimates as elements, and outputting the elements of said output vectors as demodulated data. For the above-described method, the value of M is greater than the value of R.
The present invention also provides a demodulator residing in a device, said demodulator adapted to demodulate data signal waveforms. The demodulator at least includes an input adapted to serially receive an input waveform with a symbol rate M, a serial-to-parallel multiplexer adapted to convert said input waveform into input vectors, each vector having a predetermined number of samples, and a vector demodulator adapted to, for each device clock period, where the maximum device clock speed is R, process an input vector by making soft decisions to demodulate said input vectors into output vectors containing data estimates as elements. The demodulator also at least includes a parallel-to-serial multiplexer adapted to output the elements of said output vectors as demodulated data. For the above-described demodulator, the value of M is greater than the value of R.